1. Technical Field
The present invention relates in general to a method and apparatus for testing an integrated circuit and more particularly to a built-in self-test apparatus and method for testing an integrated circuit. Still more particularly, the present invention relates to a built-in self-test apparatus and method for testing an integrated circuit which capture failure information for a selected failure.
2. Description of the Related Art
As integrated circuit technology has advanced, the complexity and density of circuit devices formed within a single chip has increased dramatically. Consequently, several problems have arisen with regard to testing such integrated circuits. For example, while the methodology for testing a memory array may be relatively straight forward, memory array chips typically have far fewer I/O pins available to a circuit tester than are required to adequately test the memory array.
A general solution to the above-described problem is to imbed test circuitry on the chip itself. Such testing facilities are frequently referred to as built-in self-test (BIST), array self-test (AST), or array built-in self-test (ABIST) circuits and will hereinafter be referred to generically as BIST circuits. With reference now to FIG. 1, there is illustrated a conventional closed-loop testing apparatus for an integrated circuit memory. As illustrated, integrated circuit (IC) 10, which includes BIST 12 and memory array 18, is coupled to IC tester 14 in a closed-loop fashion. That is, the enable/disable state of clock signal 16 is determined by feedback provided to IC tester 14 via diagnostic output (DGO) signal 20. According to the conventional BIST testing methodology, IC tester 14 scans data into BIST 12 to initialize a number of state machine latches. Then, in response to clock signal 16, BIST 12 applies internally generated test data and address data to memory array 18 and compares output data read out from memory array 18 with expected data. In response to a discrepancy between the output data and the expected data, BIST 12 indicates that a failure within memory array 18 has been detected by driving diagnostic output (DGO) signal 20 high. In response to receipt of DGO signal 20, IC tester 14 disables clock signal 16, thereby halting the state machine within BIST 12 that applies test data and address data to memory array 18. IC tester 24 then scans out the information within the state machine latches of BIST 12. Utilizing an algorithm, IC tester 14 determines the cycle in which the failure occurred from the state the state machine information and reinitializes BIST 12. Thereafter, BIST 12 is again run to the cycle in which the failure occurred by applying clock signal 16 for the appropriate number of cycles. The state machine data at the failing cycle is then scanned out by IC tester 14 and utilized to generate a bit-fail map for use in failure analysis.
The principal shortcoming of the closed-loop BIST testing methodology illustrated in FIG. 1 is the inability of IC tester 14 to test memory array 18 at typical operating speeds of fast memories (e.g., 200 MHz). Operating at 200 MHz necessitates that IC tester 14 monitor DGO signal 20 at least every 5 ns in order to capture the cycle number in which the failure of interest occurs. However, because of I/O gate delays and signal propogation delays of 1 ns/ft, the feedback provided by DGO signal 20 is too slow to indicate the cycle in which the failure of interest occurs and then stop the clocks to the BIST state machine to capture failure information.
Consequently, it would be desirable to provide an improved method and BIST apparatus for testing an integrated circuit. In particular, it would be desirable to provide a high-speed BIST apparatus and method for testing an integrated circuit which capture BIST state machine information at a selected failing cycle.